--- nand.py-
+++ nand.py
@@ -468,6 +468,21 @@
 		new_pin_n(n, self, 'out')
 		conn2_n( n, (self.and_set, 'out', 0), (self, 'out', 0) )
 
+class DESEL2(Obj):
+	# inp, A_0, out_0, out_1
+	def __init__(self, parent, name='desel2', latency=10):
+		Obj.__init__(self, parent, name)
+
+		PosiNega(self, 'posi_nega', latency)
+		Pin(self, 'A_0').conn = self.posi_nega.inp
+
+		JointANDSet(self, 2, 'jas', latency)
+		Pin(self, 'inp').conn = self.jas.inp
+		self.posi_nega.nQ.conn = self.jas.sel_0
+		self.posi_nega.Q.conn = self.jas.sel_1
+		self.jas.out_0.conn = Pin(self, 'out_0')
+		self.jas.out_1.conn = Pin(self, 'out_1')
+ 
 class GATE(Obj):
 	# inp_x, en, out_x
 	def __init__(self, parent, n, name='gate', latency=10):
@@ -522,6 +537,26 @@
 				Pin(self, nm).conn = getattr( aso, name_i('inp', i) )
 			aso.out.conn = Pin( self, name_i('out', di) )
 
+class DEMUX(Obj):
+	# sel_x, inp_dx, out_x_dx
+	def __init__(self, parent, dbit_n, n, name='demux', latency=10):
+		Obj.__init__(self, parent, name)
+
+		new_pin_n( dbit_n, self, 'inp' )
+
+		new_pin_n( n, self, 'sel' )
+		Joint_N( self, n, 'jt_sel' )
+		self.jt_sel.new_pin_conn( self, 'sel', direc='from_targ')
+
+		for i in range(dbit_n):
+			jas = JointANDSet(self, n, 'jas', latency)
+			getattr( self, name_i('inp', i) ).conn = jas.inp
+			self.jt_sel.new_pin_conn( jas, 'sel', direc='to_targ' )
+
+			for j in range(n):
+				nm = name_i('out', j)
+				getattr( jas, nm ).conn = Pin(self, name_i( nm, i ) )
+
 class ROM_D1(Obj):
 	# en, A_x, D_0
 	def __init__(self, parent, abit_n, dlst=(), name='rom_d1', latency=10):
@@ -828,7 +863,7 @@
 		c.conn = Pin(self, 'C')
 
 class ADD_DEV(Obj):
-	# en, CLK, A_0, D_x
+	# en, CLK, A_0, inp_x, out_x
 	def __init__(self, parent, dbit_n, name='add_dev', latency=10):
 		Obj.__init__(self, parent, name)
 
@@ -925,6 +960,84 @@
 		self.jt_nQ.new_pin().conn = self.and_w.inp_b
 		self.and_w.out.conn = Joint(self, 'jt_wrt', None, (x,y), 'W').new_pin()
 		self.jt_wrt.new_pin().conn = self.dev.CLK
+
+class BUS(Obj):
+	# TO_DEV, CLK, DEV_CLK_{dev#}, en, dev_en_{dev#}
+	# inp_{dev#}_{dbit#}, out_{dev#}_{dbit#}, DEV_A_{dev_abit#}, AI_{abit#}, AO_{dev#}_{abit#}, 
+	def __init__(self, parent, dbit_n, abit_n, dev_abit_n, name='bus', latency=10):
+		Obj.__init__(self, parent, name)
+
+		self.dbit_n = dbit_n
+		self.abit_n = abit_n
+		self.dev_abit_n = dev_abit_n
+		dev_n = (1 << dev_abit_n)
+
+		DESEL2(self, 'desel2', latency)
+		Pin(self, 'TO_DEV').conn = self.desel2.A_0
+		Pin(self, 'CLK').conn = self.desel2.inp
+
+
+		MUX(self, dbit_n, dev_abit_n, 'mux', latency)
+
+		Pin(self, 'en').conn = Joint(self, 'jt_en').new_pin()
+		self.jt_en.new_pin().conn = self.mux.en
+
+		new_pin_n(dev_abit_n, self, 'DEV_A')
+		conn2_n( dev_abit_n, (self, 'DEV_A', 0), (self.mux, 'A', 0) )
+
+		for i in range(dev_n):
+			nm = name_i('inp', i)
+			new_pin_n( dbit_n, self, nm )
+			conn2_n( dbit_n, (self, nm, 0), (self.mux, nm, 0) )
+
+
+		LATCH(self, dbit_n, 'latch', latency)
+
+		self.desel2.out_0.conn = self.latch.CLK
+		conn2_n( dbit_n, (self.mux, 'out', 0), (self.latch, 'inp', 0) )
+
+
+		DEMUX(self, dbit_n + abit_n + 2, dev_n, 'demux', latency)
+
+		conn2_n( dev_n, (self.mux, 'deco_out', 0), (self.demux, 'sel', 0) )
+		self.jt_en.new_pin().conn = getattr( self.demux, name_i('inp', dbit_n + abit_n) )
+
+		self.desel2.out_1.conn = getattr( self.demux, name_i('inp', dbit_n + abit_n + 1) )
+
+		conn2_n( dbit_n, (self.latch, 'out', 0), (self.demux, 'inp', 0) )
+
+		new_pin_n( abit_n, self, 'AI' )
+		conn2_n( abit_n, (self, 'AI', 0), (self.demux, 'inp', dbit_n) )
+
+		for i in range(dev_n):
+			nm = name_i('out', i)
+
+			new_pin_n( dbit_n, self, nm )
+			conn2_n( dbit_n, (self.demux, nm, 0), (self, nm, 0) )
+
+			anm = name_i('AO', i)
+			new_pin_n( abit_n, self, anm )
+			conn2_n( abit_n, (self.demux, nm, dbit_n), (self, anm, 0) )
+
+			getattr( self.demux, name_i(nm, dbit_n + abit_n) ).conn = Pin( self, name_i('dev_en', i) )
+			getattr( self.demux, name_i(nm, dbit_n + abit_n + 1) ).conn = Pin( self, name_i('DEV_CLK', i) )
+
+	def conn(self, dev_addr, dev, dev_pin_o='out', dev_pin_i='inp'):
+		abit_n = min( get_num(dev, 'A'), self.abit_n )
+		conn2_n( abit_n, (self, name_i('AO', dev_addr), 0), (dev, 'A', 0) )
+
+		if hasattr(dev, 'en'):
+			getattr( self, name_i('dev_en', dev_addr) ).conn = dev.en
+
+		if dev_pin_o:
+			dbit_n = min( get_num(dev, dev_pin_o), self.dbit_n )
+			conn2_n( dbit_n, (dev, dev_pin_o, 0), (self, name_i('inp', dev_addr), 0) )
+
+		if dev_pin_i:
+			dbit_n = min( get_num(dev, dev_pin_i), self.dbit_n )
+			conn2_n( dbit_n, (self, name_i('out', dev_addr), 0), (dev, dev_pin_i, 0) )
+			if hasattr(dev, 'CLK'):
+				getattr( self, name_i('DEV_CLK', dev_addr) ).conn = dev.CLK
 
 class Sched:
 	def __init__(self):